AMBA(Advance Microcontroller Bus Architecture) 3.0

AMBA 3 AXI to PCIe Bridge:

PLDA AMBA 3 AXI to PCI Express® Bridge is a high performance, highly-configurable, silicon-proven semiconductor IP that adds PCI Express® connectivity to AMBA 3 AXI enabled SoCs. The bridge IP is compliant to the PCI Express® rev. 2.0 specification and AMBA 3 AXI rev. 1.0 specification.

IP Features and Deliverables

AXI-PCIE Bridge

  • AMBA 3 AXI to PCI Express® Bridge IP core in synthesizable Verilog and VHDL RTL source code
    • Compliant to the PCI Express® Specification rev. 2.0
      • Includes PCI Express® Physical, Link, and Protocol layers
      • PCI Express® interface configurable as Root Port, Endpoint, or dual-mode/shared silicon
      • PCI Express® x1, x4
      • PIPE compliant Physical layer, 16-bit/125Mhz
      • 1 or 2 Virtual Channels
      • Up to 2KB Maximum Payload Size
      • 1 to 3 64-bit Base Address Registers (BAR)
      • Configurable Receive, Transmit, and Retry buffer size
      • Low power ASPM L0s and L1 for maximum power savings
      • Legacy PCI Power Management
      • MSI and INT messaging
      • AER
      • ECRC generation/check
    • Supports ExpressCard Specification
      • CLKREQ#
    • Compliant to the AMBA 3 Specification rev. 1.0
      • Includes AMBA 3 AXI bridging and interface logic
      • 64-bit AXI master and slave interfaces with 32-bit addressing
    • User defined AXI frequency
    • 2, 4, or 8 outstanding master read request and 16 write requests
    • 4, 8, or 16 outstanding slave read requests and 2, 4, or 8 write requests

AMBA: AHB, APB & AXI:

The IP for AXI, AHB, APB provides an efficient algorithm to verify the AMBA based designs by giving the advance techniques including the support for System Verilog assertions.

AMB

AXI Highlights

  • Compliant with the AMBA 3.0 AXI Protocol
  • Support all AMBA 3.0 AXI Protocol data and address width
  • Support all AMBA 3.0 AXI Protocol transfer types and response
  • Support all AMBA 3.0 AXI Protocol burst transfers
  • AXI Master and AXI slave supports multiple outstanding transactions
  • AXI Slave has the capability to respond out of order to pending transactions
  • Data interleaving is performed by both AXI master & AXI slave on write/read trasnsactions respectively
  • AXI Interconnect can support multiple AXI Masters & AXI Slaves
  • AXI Interconnect supports SASD and SAMD architechture
  • AXI Verification IP has a stand alone AXI checker which checks and reports for all protocol violations
  • Stand alone AXI checker also generates a coverage report on the check points being excercised by the testcases
  • AXI Assertions checks for signal timing violations
  • AXI monitor logs, bus traffic and generates an reports which are easy to debug from
  • AXI verification IP also includes User-configurable commands
  • AXI BFM is written in Verilog HDL and assertions in System Verilog
  • AXI verification IP has been tested with ARM protocol checker available from ARM’s website
  • Call backs and call back variables to provide control over test case execution

APB Highlights

  • Compliant with the AMBA 3.0 APB Protocol v1.0
  • Support configurable AMBA 3.0 APB Protocol v1.0 data and address width
  • Support all AMBA 3.0 APB Protocol v1.0 transfer types and response
  • APB assertion checker and APB stand alone checker checks for protocol violations
  • APB monitor logs, bus traffic and generates an reports which are easy to debug from
  • APB verification IP also includes User-configurable commands
  • APB BFM is written in Verilog HDL and assertions in System Verilog
  • Call backs and call back variables to provide control over test case execution

AHB Highlights

  • Compliant with the AMBA 3.0 AHB Protocol
  • Support configurable AMBA 3.0 AHB Protocol data and address width
  • Support all AMBA 3.0 AHB Protocol transfer types and response
  • Support AHB Protocol split and retry transfers
  • AHB Verfication IP comes with AHB arbiter to simulate multi-master and multi-slave environment
  • AHB assertion checker and AHB stand alone checker checks for protocol violation
  • AHB monitor logs, bus traffic and generates an reports which are easy to debug from
  • AHB verification IP also includes User-configurable commands
  • AHB BFM is written in Verilog HDL and assertions in System Verilog
  • Call backs and call back variables to provide control over test case execution

Product Components

  • AMBA 3.0 AXI , AHB , APB Verification Engine complaint to AMBA 3.0 specifications
  • AMBA 3.0 AXI , AHB , APB Bus Functional Models
  • Directed & Random tests generator for AMBA 3.0
  • AXI , AHB , APB comes bundled with a Compliance Test Suite
  • System verilog assertions for AMBA 3.0 AXI, AHB, APB
  • AMBA 3.0 traffic generator comes with an Error injector with complex error injection
  • AXI, AHB, APB consists of Monitor which generates detailed reports
  • AXI, AHB, APB master acts Transaction generator to simulate complex protocol scenarios
  • Protocol Checker to log violations for AXI, AHB & APB